1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to a method of fabricating an integrated circuit transistor with an improved salicidation process.
2. Description of the Related Art
Insulated gate field effect transistors ("IGFET"), such as metal oxide semiconductor field effect transistors ("MOSFET"), are some of the most commonly used electronic components in modern integrated circuits. Embedded controllers, microprocessors, analog-to-digital converters, and many other types of devices now routinely include millions of MOSFETs. The dramatic proliferation of MOSFETs in integrated circuit design can be traced to their high switching speeds, potentially low power dissipation, and adaptability to semiconductor process scaling.
A typical MOSFET implemented in silicon consists of a source and a drain formed in a silicon substrate, and separated laterally to define a channel region in the substrate. A gate electrode composed of a conducting material, such as aluminum or polysilicon, is disposed over the channel region and designed to emit an electric field into the channel region. Changes in the electric field emitted by the gate electrode enable, or alternatively, disable the flow of current between the source and the drain.
In a conventional process flow for forming a typical MOSFET, a gate oxide layer is grown on a lightly doped silicon substrate and a layer of polysilicon is deposited on the gate oxide layer. The polysilicon and the gate oxide are then anisotropically etched back to the upper surface of the substrate leaving a polysilicon gate electrode stacked on top of a gate oxide layer. Following formation of the polysilicon gate electrode, a source and a drain are formed by implanting a dopant species into the substrate. The gate electrode acts as a hard mask against the implant so that the source and drain are formed in the substrate self-aligned to the gate electrode. Many conventional semiconductor fabrication processes employ a double implant process to form the source and drain. A first implant is performed self-aligned to the gate electrode to establish lightly doped drain ("LDD") structures. After the LDD implant, dielectric sidewall spacers are formed adjacent to the gate electrode by depositing and anisotropically etching a dielectric material, such as silicon dioxide. The second of the two source/drain implants is then performed self-aligned to the sidewall spacers. The substrate is then annealed to activate the dopant in the source and the drain. Salicidation steps frequently follow the formation of the source and drain.
In conventional salicidation, titanium is deposited on the gate, the sidewall spacers, and the source and drain regions. A one or two step anneal is performed to react the titanium with the polysilicon of the gate and the silicon of the source and drain regions to form TiSi.sub.2. Following the anneal, an etch is performed to remove any unreacted titanium.
One of the principal functions of sidewall spacers is to separate the silicided gate from the source/drain regions. Despite the incorporation of spacers, silicide may form laterally and easily bridge the separation between the polysilicon gate electrode and the silicon source/drain regions causing the gate to become shorted to the source/drain regions. This so-called "bridging effect" occurs where silicon diffuses into the titanium regions that cover the sidewall spacers and subsequently reacts with the titanium.
Certain conditions tend to favor lateral TiSi.sub.2 formation. Conventional furnace annealing in an inert gas atmosphere (e.g., argon for approximately 30 minutes) may foster rapid lateral TiSi.sub.2 formation. Processing in the sub-0.25 .mu.m domain also appears to raise the frequency of lateral silicide formation. In sub-0.25 .mu.m processing, the minimum gate width may approach or even reach the dimensions of the grain boundaries between the individual grains of the polycrystalline silicon gate electrode. As the minimum device size approaches the dimensions of the grain boundaries in the polysilicon, the rate of silicon diffusion from the polysilicon into the titanium increases. The increased diffusivity is believed to stem from the elimination of pluralities of intersecting polysilicon grain boundaries that are present in larger scale processes. These grain boundaries act as natural barriers to silicon diffusion.
One method of controlling lateral TiSi.sub.2 formation used in some fabs for several years involves the introduction of a N.sub.2 ambient during the titanium anneal. Titanium absorbs a significant amount of nitrogen during the anneal, particularly at the titanium grain boundaries. The absorbed nitrogen clogs the grain boundary diffusion paths through the titanium. The result is a reduced diffusivity of silicon in the titanium and a suppression of the lateral TiSi.sub.2 reaction. A drawback of the nitrogen anneal method is the requirement for a relatively oxygen and water free nitrogen ambient (less than 5 ppma). Higher concentrations of oxygen and/or water may yield unwanted oxidation of the titanium film. Another shortcoming associated with reliance upon a nitrogen ambient is that even with the absorption of nitrogen by the titanium, bridging may still occur in sub 0.25 .mu.m processing.
Another conventional method of suppressing lateral TiSi.sub.2 formation involves careful tailoring of the anneal steps to reduce the potential for bridging. However, as is often the case in the thermal processing of integrated circuits in silicon, there are trade-offs in designing a thermal budget for a given process. Annealing titanium at higher temperatures generally produces a TiSi.sub.2 layer with a lower sheet resistance. However, higher heating tends to exacerbate the potential for lateral TiSi.sub.2 formation, and at temperatures above approximately 700.degree. C., the titanium and silicon dioxide sidewall spacers may react to form titanium oxides. Any residues of this reaction can degrade device performance by compromising the integrity of the oxide or by producing bridging. This effect tends to be less severe in rapid thermal processing anneals. Conversely, lowering the anneal temperature can reduce the potential for lateral TiSi.sub.2 formation, but often results in a higher sheet resistance for the TiSi.sub.2 layer over the source and drain, and thus a lower performance integrated circuit. In short, achieving a suitable balance between anneal temperature, acceptable TiSi.sub.2 sheet resistance, and lowered yields due to bridging is a difficult task and always subject to process variations.
The present invention is directed to overcoming or reducing one or more of the foregoing disadvantages.